An integrated circuit (“IC”) is a device (e.g., a semiconductor device) that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of signal wiring that interconnect its electronic and circuit components. Traditionally, IC's use preferred direction (“PD”) wiring models, which specify a preferred wiring direction for each of their wiring layers. In preferred direction wiring models, the preferred direction typically alternates between successive wiring layers.
One example of a PD wiring model is the PD Manhattan wiring model, which specifies alternating layers of preferred-direction horizontal and vertical wiring. Another example of a PD wiring model is the PD diagonal wiring model, which specifies alternating layers of preferred-direction diagonal wiring. The PD diagonal wiring model can allow for shorter wiring distances than the PD Manhattan wiring model and can decrease the total wirelength needed to interconnect the electronic and circuit components of an IC. The PD diagonal wiring model is described in detail in U.S. patent application Ser. No. 10/334,690, filed Dec. 31, 2002, entitled “Method and Apparatus for Routing,” incorporated herein by reference and U.S. patent application Ser. No. 10/013,819, filed Dec. 7, 2001, entitled “Routing Method and Apparatus That Use Diagonal Routes,” incorporated herein by reference.
Design engineers design IC's by transforming logical or circuit descriptions of the IC's into geometric descriptions, called layouts. IC layouts typically include (1) circuit modules (i.e., geometric representations of electronic or circuit IC components) with signal pins, and (2) interconnect lines (i.e., geometric representations of signal wiring) that connect the signal pins of the circuit modules. A signal net is typically defined as a collection of signal pins that need to be connected.
To create layouts, design engineers typically use electronic design automation (“EDA”) applications. These applications provide sets of computer-based tools for creating, editing, and analyzing IC design layouts. One EDA tool is a signal wire router that defines routes for interconnect lines that connect the signal pins of signal nets. Signal wire routing is generally divided into two phases: global signal routing and detailed signal routing. For each signal net, global signal routing generates a “loose” route for the interconnect lines that are to connect the signal pins of the signal net. The “looseness” of a global signal route depends on the particular global signal router used. After global signal routes have been created, the detailed signal routing creates specific individual routes for each signal net. A signal wire router that consistently explores diagonal routing directions (referred to herein as a diagonal wire router) is described in the aforementioned patent application titled “Method and Apparatus for Routing.”
Each IC also contains a power grid structure that provides power and ground to each electronic and circuit component of an IC. Each electronic or circuit IC component has a power pin and a ground pin that is connected to the power grid structure. A power net is typically defined as a collection of power pins that need to be connected and a ground net is typically defined as a collection of ground pins that need to be connected. The power grid structure is described in the IC layout and is later physically created for use in an IC based on the descriptions in the IC layout. As an IC includes multiple layers, an IC layout also includes descriptions of multiple layers.
Power grid structure components include stripes, rails, and vias which must be of a certain strength (i.e., size) to meet design specifications (i.e., minimum specifications that the power grid structure must meet in order to be acceptable for use in the IC). Power grid components, however, compete with signal wiring for area on an IC layer since they take up area on the IC layer that signal wiring could otherwise occupy. Also, power grid structure components can cause substantial blockage of signal wiring paths, especially on layers with the PD diagonal wiring model.
FIG. 1 illustrates a top view of a region of an IC layout having a conventional power grid structure 100. The power grid structure 100 includes stripes 105 and 107 and rails 110. Stripes 105 and 107 are typically positioned vertically (i.e., parallel to the layout's y-coordinate axis) or horizontally (i.e., parallel to the layout's x-coordinate axis) across at least one upper layer of the IC and provide power and ground to the IC. Power grid stripes that are positioned vertically or horizontally are referred to as Manhattan power grid stripes. A stripe that carries power is referred to as a power stripe 105 and a stripe that carries ground is referred to as a ground stripe 107.
Rails 110 are typically positioned horizontally (i.e., parallel to the layout's x-coordinate axis) or vertically (i.e., parallel to the layout's y-coordinate axis) across at least one lower layer of the IC. Each rail is connected to either a power stripe 105 or a ground stripe 107 through vias (not shown). Vias are positioned perpendicular to the IC's layers (i.e., parallel to the layout's z-coordinate axis) and distribute power or ground from the stripes to the rails.
Stripes 105 and 107 occupy area on a layer of the IC and can cause blocking of the signal wiring needed to interconnect the electronic and circuit components of the IC. The amount of wiring blockage varies from layer to layer depending on the PD wiring model of the layer. Conventional Manhattan power grid stripes, however, can cause near complete blockage of diagonal signal wiring. As shown in FIG. 1, a 45° diagonal direction arrow 130 and a 135° diagonal direction arrow 132 illustrate how diagonal wiring paths are blocked by stripes 105 and 107 of the conventional power grid structure 100. Therefore, there is a need for a method and apparatus for reducing the diagonal wiring blockage caused by stripes of a power grid structure while still meeting the design specifications for the power grid structure.